Integrated circuit fabrication begins with a thin, polished slice of high-purity, single crystal semiconductor, usually silicon. Junctions (which make up devices) are formed between field oxide portions of the semiconductor slice. Metal lines in conductor layers provide necessary electrical connections between the devices. Dielectric (i.e. insulating) layers are formed between the conductor layers to isolate the metal lines from each other. Vias provide conducting paths through the dielectric layers to connect interconnects of different conductor layers.
FIG. 1 is a perspective view of a portion 100 of an integrated circuit having a conventional interconnect architecture; FIG. 2 is a cross-sectional view of the integrated circuit portion 100 shown in FIG. 1; and FIG. 3 is a plane view of the integrated circuit portion 100 shown in FIGS. 1 and 2.
In the integrated circuit portion 100, two "bottom metal" strips 102a, 102b are formed in a bottom layer and two "top metal" strips 104a, 104b are formed perpendicular to the bottom metal strips 102a, 102b. Vias through a dielectric layer 108 connect the "top metal" strips to the "bottom metal" strips. In the integrated circuit portion 100 shown in FIGS. 1-3, via 106aa connects bottom metal strip 102a to top metal strip 104a; via 106ab connects bottom metal strip 102a to top metal strip 104b; via 106ba connects bottom metal strip 102b to top metal strip 104a; and via 106bb connects bottom metal strip 102b to top metal strip 104b.
As can be seen from FIGS. 1-3, in the integrated circuit portion 100 having the conventional interconnect architecture, each via is fully covered and is bordered by the top metal strip above it (overlap) and each via is also fully enclosed and bordered by the bottom metal strip below it (enclosure). Via borders provide allowance for interconnect misalignment and other process variations. That is, if a via is not fully bordered by the bottom metal strip to which it is to connect, during formation of the via, the dielectric layer, which is to insulate the bottom metal layer from the top metal layer, is attacked during etching of the vias. In extreme cases, even the devices may be attacked. Furthermore, if a via will not be fully bordered by the top metal strip to which it is to connect, the via liners can be attacked during etching of the top metal.
If the via borders required in the conventional interconnect architecture can be eliminated, increased packing density can be achieved. For example, in the conventional bordered via architecture, if the via size is 0.5 um, borders required to protect against potential via misalignment need to be at least 0.15 um. Thus, with bordered vias, the metal linewidth should be 0.8 um, the via size plus twice the via border. If the space between the metal lines at a particular level is 0.5 um, the metal pitch (linewidth+space) is 1.3 um for bottom and top metals running perpendicular to each other.